The silicon (Si) integrated circuit (IC) has dominated electronics and has helped it grow to become one of the world's largest and most critical industries over the past thirty-five years. However, because of a combination of physical and economic reasons, the miniaturization that has accompanied the growth of Si ICs is reaching its limit. The present scale of devices is on the order of tenths of micrometers. New solutions are being proposed to take electronics to ever smaller levels; such current solutions are directed to constructing nanometer scale devices.
Prior proposed solutions to the problem of constructing nanometer scale devices have involved (1) the utilization of extremely fine scale lithography using X-rays, electron, ions, scanning probes, or stamping to define the device components; (2) direct writing of the device components by electrons, ions, or scanning probes; or (3) the direct chemical synthesis and linking of components with covalent bonds. The major problem with (1) is that the wafer on which the devices are built must be aligned to within a fraction of a nanometer in at least two dimensions for several successive stages of lithography, followed by etching or deposition to build the devices. This level of control will be extremely expensive to implement. The major problem with (2) is that it is a serial process, and direct writing a wafer full of complex devices, each containing trillions of components, could well require many years. Finally, the problem with (3) is that the only known chemical analogues of high information content circuits are proteins and DNA, which both have extremely complex and, to date, unpredictable secondary and tertiary structures that causes them to twist into helices, fold into sheets, and form other complex 3D structures that will have a significant and usually deleterious effect on their desired electrical properties as well as make interfacing them to the outside world impossible.
The present inventors have developed new approaches to nanometer-scale devices, comprising crossed nano-scale wires that are joined at their intersecting junctions with bi-stable molecules, as disclosed and in U.S. Pat. Nos. 6,459,095, 6,846,682, and 6,903,366. Wires, such as silicon, carbon and/or metal, are formed in two dimensional arrays. A bi-stable molecule, such as rotaxane, pseudo-rotaxane, or catenane, is formed at each intersection of a pair of wires. The bi-stable molecule is switchable between two states upon application of a voltage along a selected pair of wires.
The present inventors have also developed new approaches to nanometer-scale interconnect arrays as disclosed in U.S. Pat. No. 6,314,019. A molecular-wire crossbar interconnect for signal routing and communications between a first level and a second level in a molecular-wire crossbar is provided. The molecular wire crossbar comprises a two-dimensional array of a plurality of nanometer-scale switches. Each switch is reconfigurable and self-assembling and comprises a pair of crossed wires which form a junction where one wire crosses another and at least one connector species connecting the pair of crossed wires in the junction. The connector species comprises a bi-stable molecule. Each level comprises at least one group of switches and each group of switches comprises at least one switch, with each group in the first level connected to all other groups in the second level in an all-to-all configuration to provide a scalable, defect-tolerant, fat-tree networking scheme. The primary advantage is ease of fabrication, because an active switch is formed any time two wires cross. This saves tremendously on circuit area (a factor of a few times ten), since no other wires or ancillary devices are needed to operate the switch or store the required configuration. This reduction of the area of a configuration bit and its switch to just the area of two crossing wires is a major advantage in constructing a defect-tolerant interconnect network.
Having developed a nanometer-scale crossbar interconnect, effective utilization requires development of logic circuits in order to construct a computer.
A prior solution presented by J. R. Heath et al, “A Defect-Tolerant Computer Architecture: Opportunities for Nanotechnology,” Science, Vol. 280, pp. 1716-1721 (12 Jun. 1998)], suggests the use of look-up tables (LUTs). These generally take up more area than programmable logic arrays (PLAs).
Thus, a need remains for high density logic circuits, employing nanometer-scale architecture.